mitsubishi semiconductor PS12012-A flat-base type insulated type jan. 2000 PS12012-A integrated functions and features ? 3-phase igbt inverter bridge configured by the latest 3rd. generation igbt and diode technologies. ? circuit for dynamic braking of motor regenerative energy. ? inverter output current capability io (note 1) : application acoustic noise-less 0.2kw/ac400v class 3 phase inverter and other motor control applica- tions. package outlines mitsubishi semiconductor PS12012-A flat-base type insulated type integrated drive, protection and system control functions: ? for p-side igbts : drive circuit, high-speed photo-couplers, short circuit protection (sc), bootstrap circuit supply scheme (single drive power supply ) and under-voltage protection (uv). ? for n-side igbts : drive circuit, short-circuit protection (sc), control supply under voltage and over voltage protection (ov/uv), system over temperature protection (ot), fault output signaling circuit (fo), and current-limit warning signal out- put (cl). ? for brake circuit igbt : drive circuit. ? warning and fault signaling : f o1 : short circuit protection for lower-leg igbts and input interlocking against spurious arm shoot-through. f o2 : n-side control supply abnormality locking (ov/uv) f o3 : system over-temperature protection (ot). cl : warning for inverter current overload condition ? for system feedback control : analogue signal feedback reproducing actual inverter output phase current (3 f ). ? input interface : 5v cmos/ttl compatible, schmitt trigger input, and arm-shoot-through interlock protection. type name PS12012-A 100% load 1.2a (rms) 150% over load 1.8a (rms), 1min (note 1) : the inverter output current is assumed to be sinu- soidal and the peak current value of each of the above loading cases is defined as : iop = io 5 ? ` 2 (fig. 1) 4- f 4 13 8.5 (7.75) 2 0.3 92.5 1 2.45 0.3 83.5 0.5 6 0.3 56 0.8 71.5 0.5 80.5 1 0.6 0.5 78.75 1.2 31 32 34 35 36 4-r4 label 33 0.5 2.5 23 1 76.5 1 20.4 1 50.8 0.8 27 1 10.16 0.3 5 (10.35) 1 cbu+ 2 cbu 3 cbv+ 4 cbv 5 cbw+ 6 cbw 7 gnd 8 vdl 9 vdh 10 cl 11 fo1 12 fo2 13 fo3 14 cu 15 cv 16 cw 17 up 18 vp 19 wp 20 un 21 vn 22 wn 23 br 31 p 32 b 33 n 34 u 35 v 36 w terminals assignment:
mitsubishi semiconductor PS12012-A flat-base type insulated type jan. 2000 ic( icp) ic(icp) i f (i fp ) cbu cbu+ cbv cbv+ cbw cbw+ gnd vdl vdh fo logic application specific intelligent power module cu cv cw cl,fo 1 ,fo 2 ,fo 3 u p v p w p v n w n b r u n b p protection circuit photo coupler input circuit drive circuit drive circuit input signal conditioning current sensing circuit protection circuit control supply fault sense r s t z : surge absorber. c : ac filter (ceramic condenser 2.2~6.5nf) [note : additionally an appropriate line-to line surge absorber circuit may become necessary depending on the application environment]. c z n m w ac 400v class line output v u brake resistor connection, ac 400v class line input inrush prevention circuit, etc. t s analogue signal output corresponding to each phase current (5v line) note 1) pwm input (5v line) note 2) note 1) to prevent chances of signal oscillation, a series resistor (1k w ) coupling at each output is recommended. note 2) by virtue of integrating a photo-coupler inside the module, direct coupling to cpu, without any extemal opto or transfo rmer isolation is possible. note 3) all outputs are open collector type. each signal line should be pulled up to plus side of the 5v power supply with appr oximately 5.1k w resistance. note 4) the wiring between power dc link capacitor and p/n terminals should be as short as possible to protect the asipm agains t catastrophic high surge voltage. for extra precaution, a small film snubber capacitor (0.1~0.22 m f, high voltage type) is recommended to be mounted close to these p and n dc power input pins. fault output (5v line) note 3) internal functions block diagram (fig. 2) v v v 900 1000 1200 applied between p-n applied between p-n, surge-value applied between p-u, v, w, br or u, v, w, br-n supply voltage supply voltage (surge) each output igbt collector-emitter static voltage condition symbol item ratings unit v cc v cc(surge) v p or v n maximum ratings (tj = 25 c) inverter part (including brake part) v p(s) or v n(s) each output igbt collector-emitter surge voltage each output igbt collector current brake igbt collector current brake diode anode current applied between p-u, v, w, br or u, v, w, br-n t c = 25 c note : ( ) means i c peak value 1200 5 ( 10) 5 (10) 5 (10) v a a a v cin v fo i fo v cl i cl i co v 7 applied between v dl -gnd supply voltage v dl symbol item ratings unit control part condition input signal voltage fault output supply voltage fault output current current-limit warning output voltage cl output current analogue-current-signal output current C0.5 ~ v dl +0.5 v v ma v ma ma applied between u p v p w p u n v n w n b r -gnd applied between f o1 f o2 f o3 -gnd sink current of f o1 f o2 f o3 applied between cl-gnd sink current of cl sink current of cu cv cw C0.5 ~ 7 15 C0.5 ~ 7 15 1 v dh , v db supply voltage v 20 applied between v dh -gnd, c bu+ -c buC , c bv+ -c bvC , c bw+ -c bwC
mitsubishi semiconductor PS12012-A flat-base type insulated type jan. 2000 t c c/w c/w c/w c/w c/w inverter igbt (1/6) inverter fwdi (1/6) brake igbt brake fwdi case to fin, thermal grease applied (1 module) junction to case thermal resistance contact thermal resistance r th(jc ) q r th(jc)f r th(jc ) qb r th(jc)fb r th(c-f) condition symbol item ratings unit (note 2) (fig. 3) 60 hz sinusoidal ac for 1 minute, between all terminals and base plate. mounting screw: m3.5 t j t stg t c v iso junction temperature storage temperature module case operating temperature isolation voltage mounting torque C20 ~ +125 C40 ~ +125 C20 ~ +100 2500 0.78 ~ 1.27 c c c vrms nm total system note 2) : the item defines the maximum junction temperature for the power elements (igbt/diode) of the asipm to ensure safe oper ation. however, these power elements can endure instantaneous junction temperature as high as 150 c. to make use of this additional temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is to be provided before use. condition symbol item ratings min. thermal resistance typ. max. 3.0 7.3 3.0 7.3 0.040 unit case temperature measurement point (3mm from the base surface) (fig. 3) ma ma v v k w 150 50 2.0 4.0 1.4 3.0 150 0.8 2.5 v dh circuit current v dl circuit current input on threshold voltage input off threshold voltage input pull-up resistor min. v m s m s m s m s m s 3.5 2.0 1.4 4.0 1.6 1.2 0.5 2.2 0.9 0.2 i dh i dl v th(on) v th(off) r i v cc 800v, input = on (one-shot) tj = 125 c start 13.5v v dh = v db = 16.5v v cc 800v, tj 125 c, ic < i ol (cl) operation level, input = on, 13.5v v dh = v db = 16.5v v fbr ton tc(on) toff tc(off) trr v ce(sat) v ec v dl = 5v, v dh = v db = 15v input = on, tj = 25 c, ic = 5a tj = 25 c, ic = C5a, input = off condition symbol item ratings typ. max. unit ? no destruction ? f o output by protection operation electrical characteristics (tj = 25 c, v dh = 15v , v db = 15v, v dl = 5v unless otherwise noted) collector-emitter saturation voltage fwdi forward voltage brake igbt collector-emitter saturation voltage brake diode forward voltage v ce(sat)br tj = 25 c, i f = 5a, input = off v dl = 5v, v dh = 15v input = on, tj = 25 c, ic = 5a switching times fwd reverse recovery time 1/2 bridge inductive, input = on v cc = 600v, ic = 5a, tj = 125 c v dl = 5v, v dh = 15v, v db = 15v note : ton, toff include delay time of the internal control circuit. short circuit endurance (output, arm, and load, short circuit modes) switching soa v dl = 5v, v dh = 15v, v cin = 5v v dl = 5v, v dh = 15v, v cin = 5v 0.3 3.6 3.5 3.6 v v v ? no destruction ? no protecting operation ? no f o output integrated between input terminal-v dh
mitsubishi semiconductor PS12012-A flat-base type insulated type jan. 2000 C1 input on voltage input off voltage pwm input frequency arm shoot-through blocking time f pwm t xx pwm input frequency allowable input on-pulse width electrical characteristics (tj = 25 c, v dh = 15v, v db = 15v, v dl = 5v unless otherwise noted) 800 supply voltage ripple applied between p-n condition symbol item ratings v cc supply voltage min. recommended conditions typ. max. unit control supply voltage d v dh , d v db , d v dl applied between v dl -gnd v dl 4.8 600 5.0 5.2 +1 v v (note 3) : (a) allowable minimum input on-pulse width : this item applies to p-side circuit only. (b) allowable maximum input on-pulse width : this item applies to both p-side and n-side circuits excluding the brake circuit. (note4) : cl output : the "current limit warning (cl) operation circuit outputs warning signal whenever the arm current exceeds this limit. the circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme. (note5) : the short circuit protection works instantaneously when a high short circuit current flows through an internal igbt ri sing up momen- tarily. the protection function is, thus meant primarily to protect the asipm against short circuit distraction. therefore, thi s function is not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due t o excessive temperature rise. instead, the analogue current output feature or the over load warning feature (cl) should be approp ri- ately used for such current regulation or over load control operation. in other words, the pwm signals to the asipm should be s hut down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back from its f o1 pin of the asipm indicating a short circuit situation. sc ot otr uv db uv dbr uv dh uv dhr ov dh ov dhr t dv i fo(h) i fo(l) i ol v dl = 5v, v dh = 15v, t c = C20 ~ 100 c (note 4) t d(read) i cl(h) i cl(l) v dh = 15v v dl = 5v t c = C20 ~ 100 c (fig.4) t int v co v c+(200%) v cC(200%) | d v co | v c+ v cC ratings 2 2 min. trip level reset level trip level reset level trip level reset level trip level reset level filter time over tenperature protection signal output cur- rent of cl operation ic = 0a ic = i op(200%) ic = Ci op(200%) allowable input signal dead time for blocking arm shoot-through t c 100 c, tj 125 c v dh = 15v, v dl = 5v, t c = C20 c ~ +100 c note 3) relates to corresponding inputs (except brake part) t c = C20 c ~ +100 c relates to corresponding inputs (except brake part) condition symbol item typ. max. unit input inter-lock sensing offset change area vs temperature idle active supply circuit under and over voltage protection idle active fault output current khz m s t dead analogue signal linearity with output current v dh = 15v, v dl = 5v, t c = C20 ~ 100 c analogue signal output voltage limit ic > i op(200%) , v dh = 15v, v dl = 5v (fig. 4) d v c (200%) analogue signal overall linear variation analogue signal data hold accuracy |v co -v c (200%) | r ch correspond to max. 500 m s data hold period only, ic = i op(200%) (fig. 5) after input signal trigger point (fig. 8) open collector onput tj = 25 c (fig. 7), (note 5) v dl = 5v, v dh = 15v t c = C20 c ~ +100 c tj 125 c open collector output 4.0 1.87 0.77 2.97 4.0 C5 3.23 5.7 100 10.0 10.5 11.05 11.55 18.00 16.50 65 2.27 1.17 3.37 15 1.1 3 1 3.90 8.0 110 90 11.0 11.5 12.00 12.50 19.20 17.50 10 1 15 500 100 2.57 1.47 3.67 0.7 5 1 4.92 11.6 120 12.0 12.5 12.75 13.25 20.15 18.65 1 m s ns v v v mv v v v % m s m a ma a a c c v v v v v v m s m a ma analogue signal reading time cl warning operation level short circuit current trip level v dh , v db control supply voltage applied between v dh -gnd, c bu+ -c buC , c bv+ -c bvC , c bw+ -c bwC v cin(on) v cin(off) f pwm t dead using application circuit using application circuit 13.5 4.8 2 4.0 15.0 10 16.5 0.3 15 v v/ m s v v khz m s
mitsubishi semiconductor PS12012-A flat-base type insulated type jan. 2000 fig. 4 output current analogue signaling linearity fig. 5 output current analogue signaling ?ata hold definition fig. 7 timing chart and short circuit protection operation 200 ?00 analogue output signal data hold range 1 2 3 4 5 400 300 100 0 ?00 ?00 ?00 0 v c +(200%) v c0 v c (200%) v c (v) v c + v c min max real load current peak value.(%)(i c =i o 5 2) v dh =15v v dl =5v t c = 20 ~ 100?c v ch (5 m s) v ch (505 m s) 0v v c 500 m s r ch = v ch (505 m s)-v ch (5 m s) v ch (5 m s) note ; ringing happens around the point where the signal output voltage changes state from ?nalogue?to ?ata hold?due to test circuit arrangement and instrumentational trouble. therefore, the rate of change is measured at a 5 m s delayed point. fig. 6 input interlock operation timing chart s c delay time short circuit sensing signal v s error output f o1 gate signal vo of each phase upper arm(asipm internal) input signal v cin of each phase upper arm 0v 0v 0v 0v note : short circuit protection operation. the protection operates with ? o flag and reset on a pulse-by-pulse scheme. the protection by gate shutdown is given only to the igbt that senses an overload (excluding the igbt for the ?rake?. 0v 0v 0v 0v 0v input signal v cin(p) of each phase upper arm input signal v cin(n) of each phase lower arm gate signal v o(p) of each phase upper arm (asipm internal) gate signal v o(n) of each phase upper arm (asipm internal) error output f o1 note : input interlock protection circuit ; it is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta- neously in ?ow?level. by this interlocking, both upper and lower igbts of this mal-triggered phase are cut off, and ? o signal is outputted. after an ?nput interlock?operation the circuit is latched. the ? o is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later.
mitsubishi semiconductor PS12012-A flat-base type insulated type jan. 2000 fig. 9 start-up sequence normally at start-up, fo and cl output signals will be pulled-up high to v dl voltage (off level); however, f o1 output may fall to low (on) level at the instant of the first on input pulse to an n-side igbt. this can happen particularly when the boot-strap capacitor is of large size. f o1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph fig. 10 recommended i/o interface circuit a) boot-strap charging scheme : apply a train of short on pulses at all n-igbt input pins for adequate charging (pulse width = approx. 20 m s number of pulses =10 ~ 500 de- pending on the boot-strap capacitor size) b) f o1 resetting sequence: apply on signals to the following input pins : br ? un/vn/wn ? up/vp/wp in that order. on on on on 0 0 0 v pn dc-bus voltage control voltage supply boot-strap voltage n-side input signal p-side input signal brake input signal f o 1 output signal v db v cin(n) v cin(p) v cin(br) f oi v dh, dl b) a) pwm starts u p ,v p ,w p ,u n ,v n ,w n ,br f o1 ,f o2 ,f o3 ,cl cu,cv,cw gnd(logic) v dl (5v) asipm cpu 10k w 5.1k w 0.1nf r r 0.1nf fig. 8 inverter output analogue current sensing and signaling timing chart. n-side igbt current n-side fwdi current t(hold) td(read) delay time +i cl ? cl on off on off 0 0 on off 0 ref v cin v(hold) i c (v s ) v c v cl
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